1. Field of the Invention
Embodiments of the present invention relate to a method for manufacturing integrated circuit devices. More particularly, embodiments of the invention relate to forming thin barrier layers using cyclic or atomic layer deposition.
2. Description of the Related Art
Copper has recently become a choice metal for filling sub-micron high aspect ratio, interconnect features because copper and its alloys have lower resistivities than aluminum. However, copper and its alloys have a propensity to diffuse into surrounding materials such as silicon oxide, silicon, and other dielectric materials for example, causing an increase in the contact resistance of the circuit. Copper and its alloys also have a propensity to diffuse into surrounding elements such as transistor gates, capacitor dielectrics, transistor wells, transistor channels, electrical barrier regions, interconnects, among other known elements of integrated circuits.
Barrier layers are, therefore, deposited prior to copper metallization to prevent or impede the diffusion of copper atoms. Barrier layers typically consist of a refractory metal such as tungsten, titanium, tantalum, and nitrides thereof, which all have a greater resistivity than copper. Of this group, tantalum nitride is one of the most desirable elements for use as a barrier layer because it has one of the lowest resistivities of refractory metal nitrides and makes a good adhesion layer for copper metallization.
To deposit a barrier layer within a feature, the barrier layer must be deposited on the bottom of the feature as well as the sidewalls thereof. Therefore, the additional amount of the barrier layer on the bottom of the feature not only increases the overall resistance of the feature, but also forms an obstruction between higher and lower metal interconnects of a multi-layered interconnect structure.
It is especially difficult to deposit a suitable barrier layer in features having aspect ratios greater than about 3:1 using conventional deposition techniques. Usually, the barrier layer bridges the opening of the narrow features resulting in the formation of one or more voids or discontinuities within the feature. Since voids increase the resistance and reduce the electromigration resistance of the feature, features having voids make poor and unreliable electrical contacts.
There is a need, therefore, for an improved method for depositing a thin, conformal barrier layer in low aspect ratio features.